(China (Mainland))
Product Summary
The CY7C342-35RC is an Erasable Programmable Logic Device (EPLD) in which CMOS EPROM cells are used to configure logic functions within the device. The MAX architecture is 100% user-configurable, allowing the CY7C342-35RC to accommodate a variety of independent logic functions. The 128 macrocells in the CY7C342-35RC are divided into eight LABs, 16 per LAB. There are 256 expander product terms, 32 per LAB, to be used and shared by the macrocells within each LAB. Each LAB is interconnected with a programmable interconnect array, allowing all signals to be routed throughout the chip.
Parametrics
CY7C342-35RC absolute maximum ratings: (1)Storage Temperature: –65℃ to +135℃; (2)Ambient Temperature with Power Applied: –65℃ to +135℃; (3)Maximum Junction Temperature (under bias): 150℃; (4)Supply Voltage to Ground Potential: –2.0V to +7.0V; (5)DC Output Current per Pin: –25 mA to +25 mA; (6)DC Input Voltage: –2.0V to +7.0V.
Features
CY7C342-35RC features: (1)128 macrocells in eight logic array blocks (LABs); (2)Eight dedicated inputs, 52 bidirectional I/O pins; (3)Programmable interconnect array; (4)Advanced 0.65-micron CMOS technology to increase performance; (5)Available in 68-pin HLCC, PLCC, and PGA packages.
Diagrams
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