(China (Mainland))
Product Summary
The EPM9320ARC208-10 in-system-programmable, high-density, high performance EPLD is based on Altera’s third-generation MAX architecture. Fabricated on an advanced CMOS technology, it provides 6,000 to 12,000 usable gates, pin-to-pin delays as fast as 10 ns, and counter speeds of up to 144 MHz.
Parametrics
Absolute maximum ratings: (1)Supply voltage With respect to ground: –2.0 to 7.0 V; (2)DC input voltage: –2.0 to 7.0 V; (3)Supply voltage during in-system programming: –2.0 to 7.0 V; (4)DC output current, per pin: –25 to 25 mA; (5)Storage temperature No bias: –65 to 150 ℃; (6)Ambient temperature Under bias: –65 to 135.
Features
Features: (1)High-performance CMOS EEPROM-based programmable logic devices (PLDs) built on third-generation Multiple Array MatriX (MAX) architecture; (2)5.0-V in-system programmability (ISP) through built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface; (3)Built-in JTAG boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990; (4)High-density erasable programmable logic device (EPLD) family ranging from 6,000 to 12,000 usable gates; (5)10-ns pin-to-pin logic delays with counter frequencies of up to 144 MHz.
Diagrams
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