EPM7192EGC160-12EM

EPM7192EGC160-12EM, PLD, PGA, Altera, –2.0V to 7.0V, –25 to 25mA

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Price:: US $21.70~24.90 / piece [Get Latest Price]

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	US $21.70~24.90

PartNumber:: EPM7192EGC160-12EM

Brand:: Altera Corporation - ALTR | Pack: PGA | D/C: 97+

Availability:: Supply Ability: 10000/Week Can Ship Immediately
Delivery: 10-15 Business Days (ships out within 3 Business days)

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Products Upload time: 2012-12-13

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Part Number:EPM7192EGC160-12EM
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Product Summary

The EPM7192EGC160-12EM is a high-density, high-performance PLD. The EPM7192EGC160-12EM is based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EPM7192EGC160-12EM provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counter speeds of up to 175.4 MHz. MAX 7000S devices in the -5, -6, -7, and -10 speed grades as well as MAX 7000 and MAX 7000E devices in -5, -6, -7, -10P, and -12P speed grades comply with the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2.

Parametrics

EPM7192EGC160-12EM absolute maximum ratings: (1)VCC Supply voltage With respect to ground:–2.0V to 7.0V; (2)VI DC input voltage: –2.0V to 7.0V; (3)IOUT DC output current, per pin: –25 to 25mA; (4)TSTG Storage temperature No bias: –65 to 150℃; (5)TAMB Ambient temperature Under bias: –65 to 135℃; (6)TJ Junction temperature Ceramic packages, under bias: 150℃; (7)PQFP and RQFP packages, under bias: 135℃.

Features

EPM7192EGC160-12EM features: (1)High-performance, EEPROM-based programmable logic devices (PLDs) based on second-generation MAXR architecture; (2)5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in MAX 7000S devices; (3)ISP circuitry compatible with IEEE Std. 1532; (4)Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S devices; (5)Built-in JTAG boundary-scan test (BST) circuitry in MAX 7000S devices with 128 or more macrocells; (6)Complete EPLD family with logic densities ranging from 600 to 5,000 usable gates (see Tables 1 and 2); (7)5-ns pin-to-pin logic delays with up to 175.4-MHz counter frequencies (including interconnect); (8)PCI-compliant devices available.