EPM9400LC84-15

Product Summary

The EPM9400LC84-15 is an in-system-programmable, high-density, high-performance EPLD. It is based on Altera’s third-generation MAX architecture. Fabricated on an advanced CMOS technology, the EPM9400LC84-15 provides 6,000 to 12,000 usable gates, pin-to-pin delays as fast as 10 ns, and counter speeds of up to 144 MHz. The EPM9400LC84-15 provides 5.0-V in-system programmability(ISP). This feature allows the devices to be programmed and reprogrammed on the printed circuit board (PCB) for quick and efficient iterations during design development and debug cycles.

Parametrics

EPM9400LC84-15 absolute maximum ratings: (1)Supply voltage:–2.0V to 7.0V; (2)DC input voltage:–2.0V to 7.0V; (3)Supply voltage during in-system programming:–2.0V to 7.0V; (4)DC output current, per pin:–25mA to 25mA; (5)Storage temperature:–65℃ to 150℃; (6)Ambient temperature:–65℃ to 135℃; (7)Junction temperature:Ceramic packages, under bias:150℃, PQFP and RQFP packages, under bias:135℃.

Features

EPM9400LC84-15 features: (1)High-performance CMOS EEPROM-based programmable logic devices(PLDs) built on third-generation Multiple Array MatriX (MAX) architecture; (2)5.0-V in-system programmability (ISP) through built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface; (3)Built-in JTAG boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990; (4)High-density erasable programmable logic device (EPLD) family ranging from 6,000 to 12,000 usable gates; (5)10-ns pin-to-pin logic delays with counter frequencies of up to 144 MHz; (6)Dual-output macrocell for independent use of combinatorial and registered logic; (7)FastTrack Interconnect for fast, predictable interconnect delays; (8)Input/output registers with clear and clock enable on all I/O pins; (9)Programmable output slew-rate control to reduce switching noise; (10)MultiVolt I/O interface operation, allowing devices to interface with 3.3-V and 5.0-V devices; (11)Configurable expander product-term distribution allowing up to 32 product terms per macrocell; (12)Programmable power-saving mode for more than 50% power reduction in each macrocell.

Diagrams