(China (Mainland))
Product Summary
The PALCE22V10H-25BLA is a 24-pin ee CMOS versatile pal device. The PALCE22V10H-25BLA provides user-programmable logic for replacing conventional SSI/MSI gates and flip-flops at a reduced chip count. The PALCE22V10H-25BLA is an advanced PAL® device built with zero-power, high-speed, electricallyerasable CMOS technology. It provides user-programmable logic for replacing conventional zeropower CMOS SSI/MSI gates and flip-flops at a reduced chip count. The PALCE22V10H-25BLA provides zero standby power and high speed. At 30 μA maximum standby current, the PALCE22V10H-25BLA allows battery-powered operation for an extended period. The PAL device implements the familiar Boolean logic transfer function, the sum of products. The PAL device is a programmable AND array driving a fixed OR array. The AND array is programmed to create custom product terms, while the OR array sums selected terms at the outputs. The product terms are connected to the fixed OR array with a varied distribution from 8 to16 across the outputs (see Block Diagram). The OR sum of the products feeds the output macrocell. Each macrocell can be programmed as registered or combinatorial, and active-high or active low. The output configuration is determined by two bits controlling two multiplexers in each macrocell.
Parametrics
PALCE22V10H-25BLA absolute maximum ratings: (1)Storage Temperature: 65°C to +150°C; (2)Ambient Temperature with Power Applied: -55°C to +125°C; (3)Supply Voltage with Respect to Ground: -0.5 V to +7.0 V; (4)DC Input Voltage: -0.5 V to VCC + 1.0 V; (5)DC Output or I/O Pin Voltage: -0.5 V to VCC + 1.0 V; (6)Static Discharge Voltage: 2001 V; (7)Latchup Current (TA = 0°C to +75°C): 100 mA.
Features
PALCE22V10H-25BLA features: (1)As fast as 5-ns propagation delay and 142.8 MHz fMAX (external); (2)Low-power EE CMOS; (3)10 macrocells programmable as registered or combinatorial, and active high or active low to match application needs; (4)Varied product term distribution allows up to 16 product terms per output for complex functions; (5)Peripheral Component Interconnect (PCI)compliant (-5/-7/-10); (6)Global asynchronous reset and synchronous preset for initialization; (7)Power-up reset for initialization and register preload for testability; (8)Extensive third-party software and programmer support; (9)24-pin SKINNY DIP, 24-pin SOIC, and 28-pin PLCC; (10)5-ns and 7.5-ns versions utilize split leadframes for improved performance.
Diagrams
